1. Field of the Invention
The present invention is directed to a bipolar transistor structure comprising a collector, a base, and an emitter in a silicon semiconductor substrate wherein the emitter zone is formed by outward diffusion from etching residues which have been produced by the deposition of conductive material onto the substrate.
2. Description of the Prior Art
The field of fast integrated circuits required in data technology, consumer electronics and communications technology, such as optical communications transmission, relies heavily upon silicon bipolar transistors.
Developments are underway to achieve higher speeds with a higher degree of integration and smaller dissipated power. There is therefore an existing need for manufacturing methods which are suitable for extremely fast memory, logic and analog circuits.
In addition to the conventional manufacturing technologies which employ adjusted masks, there are a number of methods already existing which contain self-aligning process steps and produce transistors having extremely short switching times.
The digest of technical papers of the 1982 IEEE Solid State Circuits Conference, pages 242-243, discloses a bipolar transistor structure in a report by Tang et al wherein the emitter is manufactured in a self-aligning manner relative to the base contact. The lithography of the transistor structure of 1.25 microns by 2.5 microns occurs by means of electron beam technology. The bipolar transistor structure is employed for emitter-coupled logic circuits. The spacing between emitter and base contacts is about 0.3 microns; the emitter width is at 1.25 microns.
A report by Konaka et al in the Abstracts of the 16th International Conference on Solid State Devices and Materials, 1984, pages 209-212, discloses a self-aligned bipolar transistor structure for high speed circuits, particularly in FIG. 1B wherein emitter widths of 0.35 micron are provided by electron beam lithography. The emitter zone is generated by diffusion outwardly from the emitter zone is generated by diffusion outwardly from the emitter terminal regions.
In a report by Sang-Hun Chai in the Conference Volume of the IEDM 5 disclosures a self-aligning bipolar process wherein the emitter is defined by lithography and the base zone is generated from the base terminal in self-aligning fashion by employing a vertical nitride mask. The spacing between emitter and base (0.2 micron) is determined by the layer thickness of the nitride mask. Extremely low base terminal zones of 0.2 micron are obtained. The emitter areas measure about 1.5 micron by 3.0 micron.
The methods disclosed by this prior art require a substantial investment in lithography and still do not permit emitter widths of less than 1 micron which are needed for very high speed circuits to be consistently reproduced at acceptable yield. In the prior techniques, it was not possible to manufacture largely identical transistor pairs having emitter widths less than 1 micron as required for differential amplifiers having extremely low offsets.
The known methods are accompanied by several serious disadvantages. For one, the minimum widths which were determined by the resolution of the lithography employed was additionally reduced by the internally disposed sidewall insulations or spacers arising during manufacture, as noted by the reports of Tang and Konaka. The fluctuation of the spacer width, ds, which is unavoidable in manufacture, effects a fluctuation of the emitter width by twice as much, 2ds, though the reproduceability thereof decreases greatly with extremely narrow emitters.
Secondly, since the surface of the monocrystalline emitter region was subjected to a plurality of etching steps, the risk of damage was substantial.
Third, for obvious reasons such as mechanical stresses, edge coverage, thermal stresses and the like, the spacer width was limited to various widths below 0.5 microns. Stricter demands must therefore also be met by the lithography for emitter widths below 1 micron so that the methods become extremely costly.